1. Field of the Invention
The present invention relates to a clamp circuit for clamping a voltage inputted into a signal input terminal in a semiconductor integrated circuit (IC).
2. Description of the Related Art
Recently, a large scale semiconductor IC (LSI) is manufactured in a smaller scale rule, in order to raise a response speed of the device and to reduce its chip area. Accordingly, for example, a thickness of a gate oxide film is made thinner, thereby causing such a necessity that a gate voltage be lower in order to ensure a sufficient device life and therefore, any overvoltage not be applied to the device in order to prevent a device destruction.
In order to lower the gate voltage, it is effective to employ a step-down circuit mainly used in an internal logic circuit in LSI for lowering a supply voltage. Further, in order to avoid an application of the overvoltage, it is effective to add a clamp circuit to a buffer circuit or interface circuit which is provided between the external signal input terminal and internal circuit. It is also effective to add the clamp circuit to an exterior of LSI.
FIG. 2 is an example of a conventional clamp circuit employed in an electronic control unit (ECU) of automobiles. As shown in FIG. 2, there are mounted, on a control substrate 1, a power supply IC 2 for inputting a battery voltage VB and outputting a supply voltage VDD of e.g., 5 Vxc2x15%; a control IC 3 for inputting such signals as sensor signal and communication signal and executing various controls; and an external clamp circuit 4 provided outside the IC 3.
The sensor signal inputted into a terminal 5c in a connector 5 and the communication signal inputted into a terminal 5d are further inputted through resistors R1 and R2, further through buffer circuits 6 and 7, respectively, into the control IC 3. In the exterior of the control IC 3, there are connected, between a ground 8 and terminals 5c and 5d, Zener diodes D1 and D2, respectively, of Zener voltage, e.g., 5.3 V. D1 and D2 construct the external clamp circuit 4.
Further, inside the control IC 3, there are connected diodes D3 and D4 between the ground 8 and each terminal of the buffer circuits 6 and 7, respectively, while there are connected diodes D5 and D6 between a control supply wire 9 and each terminal of the buffer circuits 6 and 7, respectively. The diodes D3 to D6 construct an internal clamp circuit 10 in the control IC 3.
Voltages inputted into the buffer circuits 6 and 7 are limited to greater than or equal to minus VF of about, e.g., minus 0.5 V and smaller than or equal to, e.g., 5.3 V, without depending upon the input signal levels. Accordingly, it becomes possible to employ MOS devices having withstand voltages of 5 V+10% (5.5 V) and minus 0.5 V which are manufactured by processes for low voltage devices. However, if the control IC 3 receives a larger number of input signals, the required number of the Zener diodes become larger, thereby increasing an area of the control substrate 1 and raising a production cost of the clamp circuit.
On the contrary, if the Zener diodes D1 and D2 are excluded, the upper voltage limit of the input signals become V+VF of about and less than 6 V, taking into consideration a fluctuation in VDD of 5 Vxc2x15%. Accordingly, the low withstand voltage device process can not be employed, but a high withstand voltage device process for, e.g., MOS having 6 V withstand voltage is required, thereby raising the production cost due to additive manufacturing processes and lowering the response speed. Further, the clamp circuits 4 and 10 have a disadvantage that the clamped voltage greatly fluctuates depending upon the temperature fluctuation.
An object of the present invention is to suppress a fluctuation of a clamped voltage due to the temperature fluctuation in a semiconductor IC.
According to the means as described in claim 1, the input voltage detecting circuit shifts by using a first transistor a level of a voltage inputted into a signal input terminal of an IC and outputs through the first resistance circuit a detected voltage. The reference voltage generating circuit shifts by using a second transistor a voltage of a second supply line and outputs through a second resistance circuit a reference voltage. The comparator compares the detected voltage with the reference voltage. The switching circuit switches on and off itself on the basis of a clamp instruction signal which is a comparison result by the comparator. Here, the detected voltage corresponds to the terminal voltage, while the reference voltage corresponds to a clamp voltage for the terminal voltage.
For example, when the higher voltage side is to be clamped, the switching circuit is switched off, if the detected voltage (terminal voltage) is smaller than or equal to the reference voltage (clamp voltage), thereby inputting the terminal voltage itself into an internal circuit formed in the IC. On the other hand, if the detected voltage (terminal voltage) is greater than the reference voltage (clamp voltage), the switching circuit is switched on, thereby lowering the terminal voltage down toward a pull-in voltage which is not greater than the clamp voltage. Then, when the terminal voltage becomes smaller than the clamp voltage, the switching circuit is switched off.
Thus, the terminal voltage can be clamped, against an overvoltage input, at a prescribed clamp voltage. According to the means as described in claim 1, only resistance elements are connected at the exterior of the IC for limiting an electric current, thereby reducing an area and cost of a substrate on which the IC is mounted.
Further, resistance circuits are connected in series with a level shift transistor both in the input voltage detecting circuit and reference voltage generating circuit, respectively. Therefore, the clamp voltage can be decided to be a prescribed voltage different from a second supply voltage by changing the resistance circuits in the input voltage detecting circuit and reference voltage generating circuit.
Further, the input voltage detecting circuit as well as the reference voltage generating circuit comprises a resistance circuit and a first and second transistors of the similar temperature characteristics, respectively. Therefore, the temperature characteristics of the detected voltage is almost the same as that of the reference voltage. Accordingly, the clamp circuit of the present invention has an advantage that the clamp voltage fluctuates little, even if the clamp circuit of the present invention is applied to such a device which is used under a wide temperature range, as an electronic control unit (ECU) for automobiles.
According to the means as described in claim 2, the clamp voltage is far more stabilized, because the total resistance value of the first resistance circuit is made equal to that of the second resistance circuit. Therefore, a temperature dependent fluctuation of the first resistance circuit becomes equal to that of the second resistance circuit.
According to the means as described in claim 3, the first and second resistance circuit are voltage divider constructed by a plurality of resistance elements. Therefore, the clamp voltage can be made to be an arbitrary value, by setting up an arbitrary voltage dividing ratio and outputting the detected voltage and reference voltage from an arbitrary voltage dividing points.
According to the means as described in claim 4, the third and fourth transistors connected between the first supply line and first and second resistance circuits, respectively, are switched on and off in accordance with an enable signal. Therefore, the current consumption in the clamp circuit can be reduced by allowing the electric currents to flow in the input voltage detecting circuit and reference voltage generating circuit only when the voltage clamping is required.
According to the means as described in claim 5, the third and fourth transistors connected between said first supply line and first and second resistance circuits, respectively, have the same characteristics, thereby supplying the input voltage detecting circuit and reference voltage generating circuit with the same bias currents. Therefore, the two circuits are balanced and the clamp voltage fluctuates little.
According to the means as described in claim 6, the input terminal voltage over a clamp voltage is clamped at the clamp voltage. Therefore, an input voltage into an A/D converter is held at a voltage at the time of starting the clamping operation, thereby obtaining a proper conversion result during the clamping operation.